1. Technical Field
The present invention is directed to an improved data processing system and in particular to an improved data cache array for utilization in a data processing system. Still more particularly the present invention relates to an improved method and system for miss sequence handling in a data cache array having multiple content addressable fields per cache line.
2. Description of the Related Art
Many systems for processing information include both a system memory and a cache memory. A cache memory is a relatively small, high-speed memory that stores a copy of Information from one or more portions of the system memory. Frequently, the cache memory is physically distinct from the system memory. Such a cache memory can be integral with the processor device of the system or non-integral with the processor.
Information may be copied from a portion of the system memory into the cache memory. The information in the cache memory may then be modified. Further, modified information from the cache memory can then be copied back to a portion of the system memory. Accordingly, it is important to map information in the cache memory relative to its location within system memory.
Generally data is mapped into a cache memory utilizing only a portion of the address of that data within the system memory. This technique provides a relatively efficient technique for locating data within a cache memory; however, the utilization of only a portion of the data address can result in several address error conditions.
For example, if the low order address bits for a selected data block are utilized to map that data block into cache memory it is possible that two different addresses may be encountered which have identical low order address bits but which represent different data addresses. This problem is generally known as an "offset" condition. In this condition the data block which is associated with a particular set of low order address bits may not be the desired data block.
Additionally, virtual address "aliasing" may occur when two different sets of low order effective address bits map to the same real address within system memory. In this situation the desired data block may be present within the data cache at a location associated with a different set of low order address bits than the low order address bits which were utilized to attempt the initial access.
It should therefore be apparent that a need exists for a method and system for miss sequence handling within a data cache which may efficiently accommodate both offset and virtual address aliasing conditions.